Conventionally, flash memories with the use of the floating gate technique have been widely used as non-volatile flash memories to be incorporated into the electronics devices. However, there are limitations for flash memory designed with the floating gate technique if the memory cell is further downsized to realize high storage density in the flash memory and the manufacturing process rule becomes equal to or smaller than 90 nm. This is because the area of the high-voltage transistor-forming region, to be provided for programming and erasing data, inevitably becomes relatively wide in a small-sized memory of the floating gate type, resulting in a rise in the manufacturing costs, or it becomes difficult to reduce a cell portion without degrading the reliability due to the possibility of memory error or data loss.
On the other hand, non-volatile memory having a thin film storage region stores a memory bit by storing the charge between two insulation films (oxide films) provided below the gate made of polysilicon. The non-volatile memory of the aforementioned thin film storage system includes SONOS (Silicon Oxide Nitride Oxide Silicon) type non-volatile memory and nanocrystal memory, in which the charge is stored in a silicon nitride film (ONO: oxide film/nitride film/oxide film) sandwiched by the silicon oxide films. The above-mentioned thin film storage method is designed so that the trap (or nanocrystal) in the nitride film may retain the charge and the stored charge is prevented from moving to another storage region. Accordingly, the above-mentioned thin film storage method has characteristics that the charge loss is suppressed and the data retention characteristics are improved, although charge loss may occur in the floating gate method.
In the technical field of non-volatile memory, there is an NROM (nitride read-only memory) having two bits/cell, a memory cell structure in which a unit cell is designed to include multiple-bits (for example, see Japanese Patent Application Publication 2001-156275 (hereinafter, referred to as “Patent Document 1”) and the cited documents therein).
FIG. 1 is a view illustrating the operation principle of NROM, and schematically shows a cross-sectional view of an NROM unit cell. The NROM cell includes first and second bit lines 12a and 12b, electrically separate from each other, which are formed by injecting an n-type dopant in regions close to the surface of a p− type conductive silicon substrate 10. A LOCOS 13 of a thin film is arranged thereon, and an ONO structure (oxide film/nitride film/oxide film) 14 is arranged on a surface region of the semiconductor substrate provided between the LOCOS 13. A word line (gate line) of polysilicon is formed so that the gate may be formed in the surface region of a semiconductor substrate 11 provided below the ONO structure 14 (below the LOCOS 13 of the thin film region). That is to say, the NROM memory cell transistor substantially has the same fundamental structure as that of a conventional n-channel MOS-FET except that an electron capture layer of the ONO structure is employed instead of a gate dielectric film.
During programming the cell of the above-mentioned NROM, for example, a given bias VG is applied to the gate line 15 and a positive bias VB2 is applied to the second bit line 12b while the first bit line 12a is grounded. Then, a channel is formed between the first bit line 12a and the second bit line 12b and electrons flowing to the second bit line 12b from the first bit line 12a are captured and stored in one end region (a second bit) 16b in the ONO structure 14.
Additionally, if the bias conditions that are applied to the first bit line 12a and the second bit line 12b are reversed, the electrons flowing to the first bit line 12a from 25 the second bit line 12b are captured and stored in the other end region (a first bit) 16a in the ONO structure 14.
In contrast, during reading the cell of the above-mentioned NROM, a given bias VG′ is applied to the gate line 15 and a positive bias VB1′ is applied to the bit line 12a while the second bit line 12b is grounded. In this manner, (the second bit) 16b can be read. Also, if the bias conditions that are applied to the first bit line 12a and the second bit line 12b are reversed, (the first bit) 16a can be read.
In addition, the width of the first bit 16a and that of the second bit 16b of the electron capture regions are designed to be sufficiently thinner than that of the channel formed between the two bit lines 12a and 12b. Hence, the two bits 16a and 16b do not affect each other, and each of the bits can be programmed and erased separately.
As described above, two pieces of bit information can be stored in the NROM by reversing the bias conditions to be applied to the first bit line 12a and the second bit line 12b. Assuming that the minimum process size is set to F, a miniaturization of 4F2 can be attained in each cell, enabling a highly integrated memory.
The minimum process size F is determined by the minimum process line width of the photolithography process, and there are the following difficulties in order to realize a cell having the area of 4F2.
When a virtual ground array structure is produced, a buried line is generally formed by the diffusion layer to be used for the source line or bit line according to the purpose thereof. However, the afore-mentioned diffusion layer is formed by ion-implantation. The implanted ions are bombarded onto the crystal lattice of the silicon substrate or diffused in the silicon crystal by thermal treatment done after the ion-implantation. This makes it difficult to downsize the width of the diffusion layer to the limit of the photolithography technique. Moreover, if a self-alignment process with the use of a hard mask is employed by providing a sidewall to overcome the aforementioned limitation in the photolithography technique, the device fabrication process will become complicated.